CAD for VLSI Design II

Overview

Syllabus 1

1. CAD for VLSI Design II
   • Transistor Theory
   • Introduction to MOSFET
   • CMOS Transistor Fundamentals
   • Transistor Theory (Contd)
   • CMOS Transistor Theory - Delay Issues
   • CMOS Transistor Theory - Delay Issues (Contd)
   • CMOS Transistor Theory - Delay Models
   • Delay Elements in CMOS Circuits
   • Delay Elements in CMOS Circuits (Contd)
   • Estimating Delays in a circuit, Issues in Dynamic and Staic Timing analysis
   • Synthesis
   • Synthesis - Synthesizable and Non Synthesizable constructs
   • Synthesis - Logic Optimization, Resource Sharing
   • Synthesis - Logic Optimization, Resource Sharing (Contd)
   • Flip Flop and Latch optimaztion
   • Introduction to Logical Effort
   • Multistage Logic Networks
   • Logical effort - Optimizing performance
   • Logical Effort and Gain based Synthesis
   • Logical Effort and Gain based Synthesis (Contd)

Advantages and disadvantages

Some points apply to every course of this kind; see how we rank.

Taught by

• Prof. Shankar Balachandran, Prof. V. KamakotiIIT Madras